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HCL Technologies: Layout Design Engineer

HCL Technologies

This is a Full-time position in Ottawa, ON posted February 8, 2021.

Qualification/Experience/Skills Required Experience: 5 to 10 years in memory layout design including building top level instances with Memory Compilers Bachelor degree in Electrical Engineering or Physics Engineering minimum Master’s Degree or PhD in Analog, Mixed-Signal or RF IC design preferred Advanced knowledge of design rules, yield and reliability issues (EM-IR, HCI and NBTI).

Should have transistor, cell and block level memory layout design hands on experience in 45nm, 28nm or lower process technology for memory layout Knowledge of CMOS semiconductor physics and microfabrication processes and impact of layout on the performance of circuitry in leading edge CMOS processes Should have sound knowledge in timing/power/leakage/functional simulation of memory instances using industry standard tools and flows Working knowledge of SKILL/PERL/TCL shell scripting languages is an asset Roles & Responsibilities
· Candidate should be technically independent, and able to work in a multi-site team environment, strong verbal & written communication skills are desired.

· This role requires 5+ years of experience Intermediate or Senior capabilities
· Good communication experience (client facing, interaction and coordination)